Comparative performance analysis of risc-v architectures: Exploring efficiency at the core

The rise of RISC-V marks a significant evolution in HPC, driven by its open-source Instruction Set Architecture (ISA), which provides unmatched modularity and customisation compared to proprietary architectures such as x86 and ARM. This study, conducted as part of the Barcelona Zettascale Laboratory (BZL) initiative, presents a comparative performance evaluation of two notable RISC-V implementations: the SiFive HiFive Unmatched and Milk-V Pioneer. Using the High-Performance Computing Challenge (HPCC) benchmark suite, the analysis explores performance under MPI and vectorised configurations, examining both intranode and internode workloads. Key metrics such as floating-point operations per cycle and memory bandwidth are assessed alongside architecture-specific features, including vector processing units (VPUs) and memory hierarchies. The findings illuminate distinct scaling patterns and performance bottlenecks, underscoring RISC-V’s potential for enabling energy-efficient and sustainable HPC solutions. These insights aim to guide future optimisations in computational throughput and support the integration of RISC-V into next-generation HPC systems prioritising energy efficiency and computational performance.